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| MOTOROLA TECHNICAL DATA Freescale Semiconductor, Inc.Rev: 2.71 Date: 15 Dec 2004 Order this document by SEMICONDUCTOR Product Preview MC33689 LIN System basis chip SILICON MONOLITHIC INTEGRATED CIRCUIT System Basis Chip with LIN transceiver The LIN SBC is a monolithic integrated circuit combining many functions frequently used by automotive LIN distributed slave nodes. It incorporates: - Single voltage regulator with low power modes - LIN physical interface. - Wake up inputs. - Triple high side driver - Current sense op amp Pin out SO32WB fine pitch Freescale Semiconductor, Inc... * Vdd: Low drop voltage regulator, current limitation, over temperature detection, monitoring and reset function, current capability 50mA. * Programmable window watchdog * Three operational modes (normal, stop and sleep modes) * Low current consumption in sleep and stop modes * LIN physical interface compatible with LIN standard. * Two external high voltage wake-up inputs * Dual high side switches, relay driver capability, internal clamp, PWM capability. * Single low current high side switch, 50mA capability for switch bias and hall sensor supply * Current sense amplifier * Nominal DC operating voltage from 5.5 to 27V * 40V maximum transient voltage * Wake up capabilities (wake up inputs, LIN interface) NC L1 NC L2 HS3 HS2 HS1 T-GND T-GND VS2 LIN GND VS1 NC Vdd aGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TX RX INT CSB MISO MOSI SCLK T-GND T-GND IN Reset Wdc e+ eOut Vcc Simplified Block Diagram Vs1 5V/50mA Vdd Vbat Voltage Regulator Reset control Reset Vs2 Window Watchdog Wdc HS1 IN HS2 SPI and Mode HS3 pre driver Control MOSI MISO SCK CSB INT L2 Vcc E- amplifier L1 E+ Vs1 Out ORDERING INFORMATION Device Operating Temperature Range Package LIN LIN Physical Interface Gnd aGnd TX RX MC33689DWB/R2 TA = -40 to 125C SO-32 This document contains information on a product under development. Motorola reserves theOn This For More Information right to change or discontinue this product without notice. Product, Go to: www.freescale.com (c) Motorola,Inc 2004 Freescale Semiconductor, Inc. MC33689 1 MAXIMUM RATINGS Ratings ELECTRICAL RATINGS Symbol Min Typ Max Unit Supply Voltage at Vs1 and Vs2 - Continuous voltage - Transient voltage (Load dump) Supply Voltage Vdd and Vcc Logic Inputs: MOSI, SCK, CSB, IN, Tx Logic output: MISO, INT, Rx, Reset Output current Vdd E+, E- input voltage V Vsupdc Vsuptr Vdd Vinlog Voutlog Idd Ve+Ie+Vout Iout -0.3 -20 -0.3 -20 -0.3 27 40 5.5 Vdd+0.3 Vdd+0.3 Internally limited 7 20 Vcc+0.3 20 V V V A V mA V mA -0.3 - 0.3 - 0.3 Freescale Semiconductor, Inc... E+, E- input current Out output voltage Out output current L1 and L2 - DC Input voltage with a 33k resistor - Transient input voltage (according to ISO7637 specification) and with external component (see figure 1 below). HS1 and HS2 output Vlxdc Vlxtr -18V -100 40 +100 V V Vhs12 internally clamped -0.3 Vs2+0.3 V HS3 LIN - DC voltage Transient input voltage (according to ISO7637 specification) and with external component (see figure 1 below). ESD voltage (HBM 100pF, 1.5k) (GND, T-GND and aGND pins connected together and configured as ground) - LIN, L1, L2 - All other pins ESD voltage (HBM 100pF, 1.5k) (GND pin configured as ground, T-GND and aGND pins as I/O) - LIN, L1, L2 - All other pins ESD voltage (Machine Model) All pins (GND, T-GND and aGND pins connected together and configured as ground) ESD voltage (Machine Model) All pins (GND pin configured as ground, T-GND and aGND pins as I/O) THERMAL RATINGS Vhs3 Vs2+0.3 V V Vbusdc Vbustr -18 -150 +40 +100 Vesdh kV -4 -2 Vesdh 4 2 kV -4 -2 Vesdm -200 4 2 200 V Vesdm -150 150 V Junction Temperature Storage Temperature Ambient Temperature (for info only) Thermal resistance junction to ambient Tj Ts Ta Rthj/a - 40 - 55 - 40 +150 +165 +85 80 C C C C/W MC33689 2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 Figure 1. : Transient test pulses for LIN and Wake pins 1nF L1 and L2 10 k Transient Pulse Generator (note) Gnd Gnd note: Waveform in accordance to ISO7637 part1, test pulses 1, 2, 3a and 3b. Freescale Semiconductor, Inc... MC33689 3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 2 ELECTRICAL CHARACTERISTICS (Vs1 and Vs2 from 5.5V to 18V and Tamb from -40C to 125C unless otherwise noted) Characteristics Description Vs1 and Vs2 pins (Device power supply) Nominal DC Voltage range Input Voltage during Load Dump Input Voltage during jump start Supply Current in Normal Mode (note 2) Supply Current in Sleep Mode (note 2) Supply Current in Stop Mode (note 2) Supply voltage fall early warning threshold VSUV flag hysteresis Supply voltage over voltage warning threshold VSOV flag hysteresis Vsup VsupLD VsupJS Isup(norm) Symbol Min Typ Max Unit Conditions 5.5 18 40 27 5 30 60 7.5 40 75 6.6 V V V mA uA uA V V Load dump situation Jump start situation (note 1) Iout at Vdd =10mA, LIN recessive state Vdd off, Vsup<=13.5V Vdd ON with Iout<100uA, Vsup<=13.5V Normal mode, INT generated, bit VSUV set guaranteed by design Normal mode, INT generated, bit VSOV set guaranteed by design Isleep Istop VSUVew VSUVhyst VSOVw VSOVhyst 5.7 6 1 Freescale Semiconductor, Inc... 18 19.25 220 20.50 V mV note 1: Device is fully functional. All functions are operating. Over temperature may occur. note 2: Total current (IVs1+IVs2) measured at gnd pins. Vdd (external 5V output for MCU supply). Specification with external capacitor 2uF Tsd 155 20 170 30 45 C C V Vsupr LR LD 3.5 20 40 150 150 mV mV note 1: measured when voltage has dropped 100mV below its nominal value. note 2: total Vdd regulator current. A 5mA current for operational amplifier operation is included. Digital output supplied from Vdd. Vdd: in Stop mode Vdd Output Voltage (note 1) Idd current capability (note 2) Line regulation Load regulation Vddstop Idds LR-s LD-s 4.75 4 5,00 8 10 40 5.25 14 100 150 V mA mV mV Idd<=2mA Stop mode 5.5V 4 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 (Vs1 and Vs2 from 5.5V to 18V and Tamb from -40C to 125C unless otherwise noted) Characteristics Description Symbol Min Reset pull down current Reset Duration after Vdd High IN: input High Level Input Voltage Low Level Input Voltage Input Current MISO: SPI output Low Level Output Voltage High Level Output Voltage Vol Voh 0 Vdd-0.9 -2 1.0 Vdd +2 V V uA I out = 1.5mA I out = -250uA 0V Tristated MISO Leakage Current MOSI, SCLK, CSB: SPI input High Level Input Voltage Low Level Input Voltage CSB Pull up current source MOSI, SCK Input Current SPI: DIGITAL INTERFACE TIMING SPI operation frequency SCLK Clock Period SCLK Clock High Time SCLK Clock Low Time Falling Edge of CS to Rising Edge of SCLK Falling Edge of SCLK to CS Rising Edge MOSI to Falling Edge of SCLK Falling Edge of SCLK to MOSI MISO Rise Time (CL = 220pF) MISO Fall Time (CL = 220pF) Time from Falling or Rising Edges of CS to: - MISO Low Impedance - MISO High Impedance Time from Rising Edge of SCLK to MISO Data Valid Freq tpCLK twSCLKH twSCLKL tlead tlag tSISU tSIH trSO tfSO tSOEN tSODIS tvalid Vih Vil Iih Iin 0.7Vdd -0.3 -100 -10 Vdd+0.3 0.3Vdd -20 10 V uA uA Vi 1V to 3.5V 0 4 N/A N/A N/A N/A N/A N/A N/A 50 50 50 50 50 MHz ns ns ns ns ns ns ns ns ns ns guaranteed by design guaranteed by design guaranteed by design 0.2 V1= 0 ns MC33689 5 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 (Vs1 and Vs2 from 5.5V to 18V and Tamb from -40C to 125C unless otherwise noted) Characteristics Description Symbol Min Typ Max Unit Conditions Figure 2. SPI Timing characteristic Tpclk CSB Tlead Twclkh Tlag SCLK Twclkl Freescale Semiconductor, Inc... Tsisu Tsih MOSI Undefined Tvalid Di 0 Don't Care Di 8 Don't Care Tsodis Tsoen MISO Do 0 Do 8 Note: Incoming data at MOSI pin is sampled by the SBC at SCLK falling edge. Outcoming data at MISO pin is set by the SBC at SCLK rising edge (after Tvalid delay time) INT: output pin Low Level Output Voltage (I0=1.5mA) High Level Output Voltage (I0=-250uA) Vol Voh 0 Vdd-0.9 0.9 Vdd V WDC: window watchdog configuration pin External resistor range Watchdog period accuracy with external resistor Watchdog period with external resistor Watchdog period with external resistor Watchdog period without external resistor, Conf pin open Rext Wdcacc Wdp 10 Wdp 100 PWdoff 97 10 -15 10.558 99.748 150 205 100 15 kohms % Excluding resistor accuracy. Note 1 R = 10 kohms. note 1 R = 100 kohms. note 1 Normal mode ms ms ms note 1: watchdog timing period calculation formula: Twd HS1 and HS2: High side output pin Rdson at Ta=25C, and Iout -150mA Rdson at Ta=125C, and Iout -150mA Rdson at Ta=125C, and Iout -120mA Output current limitation Over temperature Shutdown Leakage current Output Clamp Voltage at Iout = -100mA Ron25 Ron125 Ron3 Ilim Ovt Ileak Vcl = 0.991 * R + 0.648 (R in kohms and Twd in ms). 2 2.5 4.5 Ohms Ohms Ohms Vsup>9V Vsup>9V 5.5 mA C note 1 uA V MC33689 6 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 (Vs1 and Vs2 from 5.5V to 18V and Tamb from -40C to 125C unless otherwise noted) Characteristics Description Symbol Min Typ Max Unit Conditions note 1: when over temperature occurs, switch is turned off and latched off. Flag is set in SPI. HS3: High side output pin Rdson at Tj=25C, and Iout -50mA Rdson at Ta=125C, and Iout -50mA Rdson at Ta=125C, and Iout -30mA Output current limitation Over temperature Shutdown Leakage current Ron25 Ron125 Ron3 Ilim Ovt Ileak 60 155 100 7 10 14 200 190 10 Ohms Ohms Ohms mA C Vsup>9V Vsup>9V 5.5 uA note 1: when over temperature occurs, switch is turned off and latched off. Flag is set in SPI SENSE CURRENT AMPLIFIER SECTION: Freescale Semiconductor, Inc... Rail to rail input voltage Output voltage range Output voltage range Input bias current Input offset current Input offset voltage Supply voltage rejection ratio Common mode rejection ratio Gain bandwidth Slew rate Phase margin Open loop gain Vimc -0.1 0.1 0.3 Vcc+0.1 Vcc-0.1 Vcc-0.3 250 V V V nA nA mV dB dB Guaranteed by design Guaranteed by design Guaranteed by design Output current +- 1mA Output current +-5 mA Vout1 Vout2 Ib Io Vio SVR CMR -100 -15 60 70 1 0.5 40 85 100 15 GBP SR PHMO OLG Mhz V/us dB For gain=1,load 100pF// 5kohms. Guaranteed by design Guaranteed by design L1, L2 inputs Negative Switching Threshold Vthn 2 2.5 2.7 2.7 3 3.5 0.5 -10 8 20 2.5 3 3.2 3.3 4 4.2 3 3.5 3.7 3.8 4.5 4.7 1.3 10 38 V 5.5V Vthp V Hysteresis Input current Wake up Filter Time STATE MACHINE TIMING Delay between CSB low to high transition (at end of SPI stop command) and Stop mode activation (Guaranteed by design) Interrupt low level duration Internal oscillator frequency accuracy Normal request mode time out Delay between SPI command and HS1, HS2 or HS3 turn on (note 1, 2) Delay between SPI command and HS1, HS2 or HS3 turn off (note 1, 2) Delay between Normal Request and Normal mode, after W/D trigger command Delay between CSB wake up (CSB low to high) and SBC normal request mode (Vdd1 on & reset high) Vhyst Iin Twuf V uA us Tstop-m Tstop-nw Tstop-M Tint Osc-f1 NRtout Ts-HSon Ts-HSoff Ts-NR2N 1.4 6 12 7 -35 97 150 10 5 30 50 13 35 205 20 20 us us us us % ms us us us Minimum Watchdog period No watchdog selected Maximum watchdog period All modes, for info only Normal request mode Normal mode Vsup>9V, Vhs >= 0.2 Vs1 Normal mode Vsup>9V, Vhs <= 0.8 Vs1 Normal request mode, Guaranteed by design SBC in stop mode 6 35 30 Tw-csb 15 40 80 us MC33689 7 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 (Vs1 and Vs2 from 5.5V to 18V and Tamb from -40C to 125C unless otherwise noted) Characteristics Description Delay between CSB wake up (CSB low to high) and first accepted SPI command Delay between INT pulse and 1st SPI command accepted The minimum time between two rising edges on the CSB Symbol Min Tw-spi Ts-1stspi T2csb 90 30 15 Typ Max N/A N/A us us us SBC in stop mode In stop mode after wake up Unit Conditions note 1: when IN input is set to high, delay starts at falling edge of clock cycle #8 of the SPI command and start of device activation/deactivation. 30mA load on HS switches. Excluding rise or fall time due to external load. note 2: when IN used to control HS switches, delays measured betxween IN and HS1 or HS2 on /off. 30mA load on HS switches. Excluding rise or fall time due to external load. Rx: LIN physical layer output Low Level Voltage Output Vol Voh 0 3.75 0.9 5.25 V V I in +1.5mA I out 250uA Freescale Semiconductor, Inc... High Level Voltage Output Tx: LIN physical layer input Low Level Voltage Input High Level Voltage Input Input Threshold Hysteresis Pull-up Current Source Vil Vih Vinhyst Is 3.5 50 -100 550 1.5 V V 800 -20 mV uA 1V kohms external bus pull 500 Ohms Recessive state In normal mode. In sleep and stop mode if not turned off by SPI In sleep and stop mode with 30k disconnected Pull up current source Over current shutdown threshold Over current shutdown delay Leakage Current to GND Gnd disconnected, Vgnd = Vsup, VLin at -18V Leakage Current to GND, Vsup Disconnected, VLin at +18V Lin Receiver Vil (Tx high, Rx low) Lin Receiver Vih (Tx high, Rx high) LIN Receiver Threshold center LIN Receiver Input Hysteresis LIN wake up threshold Ipu Iov-cur Iov-delay Ibus-pasrec Ibus no gnd Ibus Lin-vil Lin-vih Lin-thres LIN hyst LIN wu 0 0.6 VSUP 0.475 0 -1 50 1.3 75 10 3 20 1 1 10 0.4VSUP VSUP 0.5 0.525 0.175 0.5 150 uA mA us uA mA uA Vsup disconnected Vlin at +18V Guaranteed by design Recessive state, Vsup 8V to 18V, Vlin 8V to 18V Vsup Vsup Vsup (Lin-vih - Lin-vil) / 2 Lin-vih - Lin-vil LIN physical layer: bus driver timing characteristics for normal slew rate (note 1) Dominant propagation delay Tx to LIN Dominant propagation delay Tx to LIN Recessive propagation delay Tx to LIN Recessive propagation delay Tx to LIN Prop delay symmetry: tdom min - trec max tdom min tdom max trec min trec max dt1 -10.44 50 50 50 50 us us us us us Measurement threshold 58.1% Vsup Measurement threshold 28.4% Vsup Measurement threshold 42.2% Vsup Measurement threshold 74.4% Vsup MC33689 8 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 Prop delay symmetry: tdom max - trec min dt2 11 us note 1: Vsup from 7V to 18V, bus load R0 and C0 1nF/1k, 6.8nF/660, 10nF/500. Measurement thresholds: 50% of Tx signal to LIN signal threshold defined in the column "condition" LIN physical layer: bus driver timing characteristics for slow slew rate (note 1) Dominant propagation delay Tx to LIN Dominant propagation delay Tx to LIN Recessive propagation delay Tx to LIN Recessive propagation delay Tx to LIN Prop delay symmetry: tdom min - trec max Prop delay symmetry: tdom max - trec min tdom min tdom max trec min trec max dt1s dt2s -22 100 100 100 100 23 us us us us us us Measurement threshold 61.6% Vsup Measurement threshold 25.1% Vsup Measurement threshold 38.9% Vsup Measurement threshold 77.8% Vsup Freescale Semiconductor, Inc... note 1: Vsup from 7V to 18V, bus load R0 and C0 1nF/1k, 6.8nF/660, 10nF/500. Measurement thresholds: 50% of Tx signal to LIN signal threshold defined in the column "condition" LIN physical layer: bus driver fast slew rate LIN high slew rate (programming mode) Dv/Dt fast 13 V/us Fast slew rate LIN physical layer: receiver characteristics and wake up timings Receiver dominant propagation delay Receiver recessive propagation delay Receiver prop delay symmetry Bus wake up deglitcher Bus wake up event reported TrL TrH Tr-sym TpropWL Twake -2 30 70 20 3.5 3.5 6 6 2 90 us us us us us LIN low to Rx low. Note 2 LIN high to Rx high. note 2 TrL - TrH Sleep and stop mode Note 3 note 2: Measured between LIN signal threshold "Lin-vil" or "Lin-vih" and 50% of Rx signal. note 3: Twake is typically 2 internal clock cycles after LIN rising edge detected. Ref to "LIN bus wake up behavior" figure. In sleep mode the Vdd rise time is strongly dependant upon the decoupling capacitor at Vdd pin. Figure 3. Test circuit for timing measurements Vsup Vsup Tx LIN Rx Gnd C0 R0 R0 and C0: 1k/1nF, 660ohms/6.8nF and 500ohms/10nF MC33689 9 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 Figure 4. timing measurements for normal slew rate Tx recessive state Vrec LIN Tdom min 58.1% Vsup 40% Vsup 28.4% Vsup Tdom max Trec max 74.4% Vsup 60% Vsup 42.2% Vsup Trec min Freescale Semiconductor, Inc... Rx TrL TrH Figure 5. timing measurements for slow slew rate Tx recessive state Vrec LIN Tdom min 61.6% Vsup 40% Vsup 25.1% Vsup Tdom max Trec max 77.8% Vsup 60% Vsup 38.9% Vsup Trec min Rx TrL TrH Figure 6. LIN bus wake up behavior SBC in sleep mode recessive level Vsup LIN 0.4Vsup dominant level Vdd INT recessive level Vsup LIN 0.4Vsup dominant level SBC in stop mode TpropWL Twake TpropWL Twake MC33689 10 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 3 STATE MACHINE Vddlow (150ms) expired and VSUV = 0 Vdd high & Reset counter (1ms) expired & W/D not selected Vdd high & Reset counter (1ms) expired & W/D selected Reset SBC power up Vdd low OR (NR time out occurs (150ms) & W/D selected) Normal Request W/D trigger Freescale Semiconductor, Inc... Power Down Vdd low OR (W/D fail & W/D selected) Normal Sleep command Stop command Vdd low Wake up Wake up Stop Sleep W/D selected means: external resistor between Wdc pin and gnd or Wdc pin open. W/D not selected means Wdc pin connected to gnd. W/D fail means: W/D trigger occurs in closed window or no SPI W/D trigger command. Stop command means: SPI stop command. Sleep command means: SPI sleep request followed by SPI sleep command. Wake up means: L1 or L2 state change or LIN bus wake up or CSB rising edge. MC33689 11 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 4 PIN DESCRIPTION pin name Vs1 Vs2 GND aGND T-GND Vdd Reset Wdc Tx Rx LIN HS1, HS2, HS3 L1, L2 Vcc EE+ Out MOSI MISO SCLK CSB INT IN Table 4-1. Pin number 13 10 12 16 8,9,24,25 15 22 21 32 31 11 7,6,5 2,4 17 19 20 18 27 28 26 29 30 23 function Power supply pin. Supply for the voltage regulator and the internal logic. Power supply pin. Supply for the high side switches. Electrical ground pin pins for the device. Analog ground pin for voltage regulator and sense amplifier. Thermal ground pins for the device 5V regulator output. Reset output Configuration pin for the watchdog. A resistor is connected to this pin.The resistor value defines the watchdog period. If the pin is open, the W/D period is fixed (default value). If this pin is tied to gnd the watchdog is disabled. Transmitter input of the LIN interface Receiver output of the LIN interface LIN bus line High side driver output 1, output 2 and output 3 Wake input 1, wake up input 2 5V supply input of operational amplifier Inverted input of the sense amplifier Non inverted input of the sense amplifier Output of the sense amplifier SPI: Master Out Slave In pin SPI: Master In Slave Out SPI: Clock input pin SPI: Device chip select pin Interrupt output pin AND wake up event signalling in stop mode. Direct input for PWM control of High Side switches 1 and 2 Freescale Semiconductor, Inc... MC33689 12 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 5 GENERAL DESCRIPTION The LIN SBC is an integrated circuit dedicated to automotive applications. It includes the following functions: - One full protected voltage regulator with 50mA total output current capability available at Vdd external pin, with under voltage reset function. - Programmable window watchdog function, INT output - Wake up from Lx wake input and LIN bus - LIN physical interface - Two 150mA high side protected switches PWM capable for relay or lamp drive - One 50mA high side protected switch for hall sensor or - Current sense op amp Device Supply The device is supplied from the battery line through the Vs1 and VS2 pins. An external diode is required to protect against negative transients and reverse battery. It can operate from 4.5V and under the jump start condition at 27V DC. Device functionality is guaranteed down to 4.5V at VS1 and VS2 pins. This pin sustains standard automotive voltage conditions such as load dump at 40V. Over and under voltage warning. If the voltage at VS1 exceed 20V typical or falls below 6V typical, the device generates an INT. VSOV or VSUV bits are set in the SPI register. Information is latched until the bit is read AND the fault has disappeared. The interrupt is not maskable. 5.3 5.4 LIN physical interface: The device contains an integrated LIN physical interface. 5.2 5.1 Freescale Semiconductor, Inc... L1 and L2 inputs: These pins are used to sense external switches and to wake up the device from sleep or stop mode. During normal mode the state of these pins can be read through SPI. HS1 and HS2: These are two high side switches to drive load such as relays or lamps. They are protected against over current and over temperature and include internal clamp circuitry for inductive load drive. Control is done through SPI. PWM capability is offered through the IN input. If PWM control is required, the internal circuitry which drive the internal high side switch is an AND function between the SPI bit HS1 (or HS2) and the IN input. In order to have HS1 on, bit HS1 must be set and IN input must be tied to a micro controller PWM ouptut to generate the PWM control signal (HS1 on when IN is high, HS1 off when IN is low). Same for HS2 output. If not PWM control is required, IN input must be connected to Vdd or to a high logic level, then the control of HS1 and HS2 is done through SPI only. If over temperature occurs on any of the 3 switches, the faulty switch is turned off and latched off until HS1 (or HS2 or HS3) bit is set to 1 in the SPI register. The failure is reported through SPI by HSst bit. 5.6 5.7 5.8 HS3: This high side switch can be used to drive small lamps, hall sensor or switch pull up resistors. Control is done through SPI Sense amplifier: E+, E- and OUT are the 3 terminations of the current sense amplifier. The amplifier is enable in normal mode only. Mode of operation Mode are controlled by the mode1 and mode 2 bits in the SPI register. 3 modes are available: sleep, stop and normal. 5.5 The operation modes and the associated functions are described in the table below. HS1 HS2 HS3 Operational amplifier Not active Device Mode Voltage Regulator Wake up capabilities Reset output Watchdog function LIN interface Reset Vdd: ON N/A Low for typ 1ms, then high (if Vdd above threshold) - High. - Active low if Vdd under voltage occurs and if Normal Request timeout (if W/D enable) Disable OFF Recessive only Normal Request Vdd: ON N/A 150ms time out if W/D enabled. ON or OFF Transmit and Receive Not active Table 5-1. MC33689 13 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 Device Mode Voltage Regulator Wake up capabilities Watchdog function HS1 HS2 HS3 LIN interface Operational amplifier Reset output Normal Vdd: ON N/A - High. - Active low if Vdd under voltage occurs or if W/D fail (if W/D enable) - Normally high. - Active low if Vdd under voltage occurs - Low - Go to high after wake up and Vdd within spec Window WD if enabled. ON or OFF Transmit and Receive Recessive state with Wake capability Recessive state with Wake capability Active Stop Vdd ON, limited current capability Vdd OFF, (Set to 5V after wake up to enter Normal request) LIN and state change on Lx inputs LIN and state change on Lx inputs Disable OFF Not active Sleep Disable OFF Not active Freescale Semiconductor, Inc... Table 5-1. Sleep and stop mode enter: To safely enter sleep or stop mode and to ensure that these modes are not entered by noise issue during SPI transmission, a dedicated sequence combining bit controlling the LIN bus and the device mode must be send twice. Enter sleep mode: first and second SPI commands (with bit D6=1, D7=1, D5 =0 or 1, D1=0 and D0=0) 11x0_0000 must be sent. Enter stop mode: first and second SPI commands (with bit D6=1, D7=1, D5 =0 or 1, D1=0 and D0=1) 11x0_0001 must be sent. Sleep or stop mode is entered after the second SPI command. D5 bit must be set accordingly. 5.9 Window watchdog. The window watchdog is configurable using external resistor at Wdc pin. The W/D is cleared through mode1 and mode 2 bit is SPI register. If Wdc pin is left open a fixed watchdog period is selected (typ 150ms). If no watchdog function is required or to disable the watchdog, the Wdc pin must be connected to gnd. The watchdog period is calculated by the following formula: Twd = 0.991 * R +0.648 (with R in kohms and Twd in ms). window closed no watchdog clear allowed window open for watchdog clear Twd * 50% Twd * 50% Watchdog period Twd Window watchdog operation Watchdog clear: The watchdog is cleared by SPI write command with following mode1 and mode2 bits. Mode 2 0 0 1 1 Mode 1 0 1 0 1 Mode Sleep mode (note 1) Stop mode Normal mode + W/D clear (note 2) Normal mode MC33689 14 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 Note 1: Special SPI command and sequence is implemented in order to avoid to go into sleep or stop mode with a single 8 bit SPI command. Note 2: When a zero is written to "Mode1" bit while "Mode2" bit is written as a one, after the SPI command is completed "Mode1" bit is set to one and SBC stays in normal mode. In order to set the SBC in sleep mode, both "Mode1" and "Mode2" bits must be written in the same 8 bits SPI command. The W/D clear on normal request mode (150ms) has no window. 5.10 INT pin: This pin is used to report fault to the MCU. Int pulse is generated in case of: - Vdd regulator temperature pre warning - high side switch 1, 2 or 3 thermal shutdown - Vsup over voltage (20V typ) - Vsup under voltage (6V typ). If an INT is generated, when the next SPI read operation is performed bit D7 is set to 1. This mean that the bits (D6 to D0) report the interrupt source. In case of wake up from stop mode, INT is set low in order to signal to the MCU wake up event from L1, L2 or LIN bus. Freescale Semiconductor, Inc... MC33689 15 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 6 6.1 SPI INTERFACE AND REGISTER DESCRIPTION Data format description Bit7 MISO D7 Bit6 D6 Bit5 D5 Bit4 D4 Bit3 D3 Bit2 D2 Bit1 D1 Bit0 D0 MOSI The SPI is an 8 bits SPI. All bits are data bytes. The MSB is send first. The minimum time between two rising edges on the CSB pin is 15us. During an SPI communication the state of MISO reports the state of the SBC, at time of CSB high to low transitions. The status flag are latched at CSB high to low transitions. Following tables describe the SPI register bit meaning, "reset value" and "bit reset condition". D7 W R Write Reset value Write Reset condition LINSL2 INT source 0 POR, RESET D6 LINSL1 LINWU or LINFAIL 0 POR, RESET D5 LIN-PU VSOV D4 HS3 VSUV BATFAIL (note1) 0 POR, RESET D3 HS2 VddT D2 HS1 HSst D1 Mode2 L2 D0 Mode1 L1 Freescale Semiconductor, Inc... 0 POR 0 POR, RESET 0 POR, RESET - - Note 1: The first SPI read, after reset, returns the BATFAIL flag state on bit D4. D7 signals INT source. After INT occur, D7 read as a "1" means other bits report the INT source. D7 read as a "0" mean no INT occurred and other bit report real time status. 6.2 6.2.1 Write control bits: Mode control bits: Mode 2 0 0 1 1 6.2.2 High side switches control bits: HS1 0 1 6.2.3 Description HS1 off HS1 on (if IN = 1) Mode 1 0 1 0 1 Description Sleep mode Stop mode Normal mode + W/D clear Normal mode HS2 0 1 Description HS2 off HS2 on (if IN = 1) HS3 0 1 Description HS3 off HS3 on LIN pull up termination control bits: LIN-PU 0 1 Description 30k pull up connected in sleep and stop mode 30k pull up disconnected in sleep and stop mode MC33689 16 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 6.2.4 LIN slew rate control and device low power mode pre selection: LINSL2 0 0 1 1 LINSL1 0 1 0 1 Description Lin slew rate normal (baud rate up to 20kb/s) Lin slew rate slow (baud rate up to 10kb/s) Lin slew rate fast (for program download, baud rate up to 100kb/s) Low power mode (sleep or stop mode) request, no change in LIN slew rate 6.3 6.3.1 Read control bits: Switch input wake up and real time status: L2 0 1 Description L2 input low L2 input high or wake up by L2 (first register read after wake up) L1 0 1 Description L1 input low L1 input high or wake up by L1 (first register read after wake up) Freescale Semiconductor, Inc... 6.3.2 High side switch, voltage regulator and device supply status VSUV BATFAIL 0 1 HSst 0 1 Description HS no over temp HS1,2 or 3 OFF (over temp) LIN bus status LINWU LINFAIL 0 1 VddT 0 1 Description No over temperature Vdd over temperature pre warning Description Vsup above 6V Vsup below 6V VSOV 0 1 Description Vsup below 19V Vsup above 18V 6.3.3 Description No LIN bus wake up of failure LIN bus wake up occurred or LIN over current of over temperature 6.3.4 Interrupt status INT mask 0 1 Description SPI word read reflects the flag state SPI word read reflects the interrupt or wake up source MC33689 17 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC33689 Freescale Semiconductor, Inc... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typical" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or un authorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the parts. Motorola and an Equal Employment Opportunity/Affirmative Action Employer. are registered trademarks of Motorola, Inc. Motorola, Inc. is How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Technical Information Center: 1-800-521-6274 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-344-3569 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 HOME PAGE: http://www.motorola.com/semiconductors MC33689 18 For More Information On This Product, Go to: www.freescale.com |
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